Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. A typical FPGA architecture (for example, a Virtex FPGA available from Xilinx Inc. of San Jose Calif.), includes an array of configurable logic blocks (CLBs), a programmable interconnect structure, and programmable input/output blocks (IOBs). Each of the CLBs, the programmable interconnect structure, and the IOBs includes configuration memory cells, the contents of which determine how the CLB, the programmable interconnect structure, or the IOB is configured. To realize a user-defined circuit, configuration data is loaded into the configuration memory cells such that the CLBs and IOBs and programmable interconnect are configured to realize particular circuit components used in the user-defined circuit.
The configuration memory cells on the FPGA may, for example, be loaded from a frame shift register. In such a case, a stream of configuration data bits is typically serially loaded into the frame shift register, and then each configuration memory cell is loaded with an appropriate configuration data bit from the frame shift register. The part of the FPGA circuitry that is configurable to realize the user-defined circuit is referred to here as the “configurable logic portion”. The part of the FPGA circuitry (for example, the configuration memory cells) that stores and supplies the configuration data bits to the configurable logic portion is referred to here as the “configuration memory”. Often an external memory device such as a programmable read only memory (PROM) is disposed on a printed circuit board along with the FPGA such that on power up of the FPGA, configuration data stored in the PROM is serial loaded into the configuration memory of the FPGA such that the FPGA is configured to realize the user-defined circuit.
FIG. 1 (Prior Art) is a simplified conceptual diagram of an SRAM-based FPGA 1. Square 2 represents a configuration memory cell of the configuration memory 3 of FPGA 1. Configuration memory cell 2 stores a configuration data bit that configures a pass transistor 4 of a programmable interconnect structure of the configurable logic portion 5 of FPGA 1. Both the configuration memory 3 and the configurable logic portion 5 of FPGA 1 are disposed on a single integrated circuit die. Typically the configuration memory of an FPGA occupies about one third of the total die area of the FPGA.
A user-defined design may involve more circuit functionality than can be realized on a single FPGA integrated circuit. It would be desired to increase the size of the FPGA integrated circuit to be able to provide circuitry to realize this functionality, but the maximum size of the FPGA integrated circuit is limited by current semiconductor processing technology. An integrated circuit whose size is limited in this way is sometimes referred to as “reticle-limited”. It is therefore desired to be able to increase the amount of integrated circuit area available for the FPGA beyond the maximum amount available in a reticle limited FPGA integrated circuit. Also, it may be difficult to produce a large complex integrated circuit without defects. The yield of such large devices may be low, causing these devices to be very expensive to produce. A solution is desired.